> For the complete documentation index, see [llms.txt](https://exobrain.stfwn.com/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://exobrain.stfwn.com/computer-science/basic-architecture-and-assembly.md).

# Basic Architecture and Assembly

## Core parts

* **Program Counter (PC):** counts which instruction is executed.
* **Instruction Memory (IM):** stores instructions.
* **Registers:** holds bitvectors that represent values, such as the results of

  instructions. Every vector has a unique address.
* **Arithmetic Logic Unit (ALU):** performs calculations.

## Basic commands

The ALU performs calculations on two input numbers called *register source* `rs` and `rt` (a name owed to the fact that *t* comes after *s*). The result is stored in *register destination* `rd`. The instructions for the ALU consist of an *opcode* that specifies the operation and the contents of `rs` and `rt`.

| Instruction    | Meaning                              |                 |
| -------------- | ------------------------------------ | --------------- |
| `ADD rd rs rt` | `+` (add)                            |                 |
| `SUB rd rs rt` | `-` (subtract)                       |                 |
| `AND rd rs rt` | `&` (bitwise AND)                    |                 |
| `OR rd rs rt`  | \`                                   | \` (bitwise OR) |
| `XOR rd rs rt` | `^` (bitwise XOR)                    |                 |
| `SHL rd rs rt` | `<<` (bit shift left)                |                 |
| `SHR rd rs rt` | `>>` (bit shift right)               |                 |
| `COPY rd rt`   | Copy `rt` to `rd` (`rs` is ommitted) |                 |

In every instruction, `rt` can be replaced with an *immediate* `imm`, a constant that is stored in the Instruction Memory (IM). To signify this option 'I' is appended to the instruction abbreviation, except in `COPY`, of which the `imm` variant is named `LOADI`. E.g.: `ADD rd rs rt` becomes `ADDI rd rs imm`. `COPY`'s immediate-variant is `LOADI`, with syntax `LOADI rd imm`. Using an `imm` instead of `rt` is done via a signal *SecReg* which regulates a mux (multiplexer/switch) that decides if the *second register* `rt` is used (SecReg = 1) or the immediate `imm` (SecReg = 0).

## Branch instructions

The ability to jump from one instruction to the next non-linearly is needed for more complex control flow. This requires some extra hardware:

* An extra output on the ALU: **Zero**. This outputs `1` if the ALU's regular

  output is logically evaluated as 0 (i.e. all bits are zero) and `0` if not

  (not all bits are zero).
* The opcode is expanded with two bits: a **branch**-bit and an **invert**-bit.
* These three new bits of information are combined into a bit named **LOADPC**

  by way of the formula: `LoadPC = Branch AND (Zero XOR Invert)`.
* LoadPC is connected to the Program Counter. If `LoadPC == 1`, the counter

  will take the value: `new address = current address + offset`. The offset

  value comes stems from the instruction.

| Instruction       | Meaning                                 |
| ----------------- | --------------------------------------- |
| `BZ rt label`     | Branch if `rt == 0` (Branch Zero)       |
| `BNZ rt label`    | Branch if `rt != 0` (Branch Not Zero)   |
| `BEQ rs rt label` | Branch if `rs == rt` (Branch EQual)     |
| `BNE rs rt label` | Branch if `rs != rt` (Branch Not Equal) |
| `BRA label`       | BRanch Always (unconditional)           |

{% hint style="info" %}
`label` is an abstract reference to an instruction here. Depending on the flavor of assembly, you may write an absolute address, which is then automatically translated into the correct offset. The offset is ultimately the value that is worked with in the hardware as described here.
{% endhint %}